The present invention is directed generally to digital systems, and more particularly to a clock synchronization system for developing a clock signal synchronized to a reference signal.
Much, if not all, of today's computing systems are synchronous machines; that is, machines in which decisions are made, events happen, and activity occurs in response to transitions of a periodic clock signal. It is often necessary, therefore, that a periodic clock signal be variously distributed to a large number of clocked devices (e.g., counters, latches, flip-flops, etc.) located throughout the system. And, as the size of the computing system increases, distribution of a single clock signal to the system elements can present problems. These problems are exacerbated when the operating frequencies of the system increase.
One approach has been use a number of driver elements, all of which receive the clock signal, to thereby develop a plurality of clock signals that are then distributed throughout the system as the system clock. This approach works well at lower system speeds. However, it has serious limitations when used in high performance systems. As the operating frequency of the system approaches 20-40 MHz and above, clock skew becomes a significant consideration. Past distribution schemes, such as that described above, can limit the speed with which the digital system will operate. Destination loading, lead lengths, and parasitic factors will introduce propagation delay, edge degradation, and the like, ultimately resulting in the distributed signal being delayed or "skewed" relative to the original when it reaches its ultimate destination. This skew must be taken into effect during design and operation, limiting system speed.
Certain clock distribution schemes have been realized with commercially available parts, either in discrete or integrated form, but with limited success. Those clock distribution schemes implemented in discrete elements (e.g., individual transistors and resistors) will usually impart unacceptable (and unequal) propagation delays and output skews. The clock distribution schemes using elements in integrated form will, of course, use circuit elements often manufactured under different processing conditions, and therefore most likely will exhibit different operating characteristics (i.e., minimum and maximum delay differences, etc.). Further, when the distribution circuitry is implemented in circuit parts different from that generating and using the clock signals, the variances due to temperature or voltage fluctuations may differ from part to part.
Further still, to form the necessary number of clock distribution buffers/drivers on a single integrated circuit chip can lead to significant noise problems (e.g., delta I or ground bounce) caused principally by the parasitic inductive path to ground. This type of problem is exacerbated in larger systems requiring a larger clock distribution network.
Other, more exotic clock distribution schemes have also been proposed and implemented, such as those employing GaAs laser diodes with fiber optic distribution. However, the cost of implementing these non-standard clock circuits can be prohibitive, and often entail considerable technical risk.
The end result of presently available clock distribution is that the various of the plurality of clock signals distributed to perform the synchronous operations in a computing system will not be synchronous to one another; that is, the various unwanted electrical characteristics encountered in known distribution schemes, such as those referred to above, will limit the operating speed of today's computing systems. The various clock signals that are distributed throughout the system must have transitions (i.e., LOW to HIGH or HIGH to LOW) that are within an acceptable range of one another. More time must be given to ensure that the clocked circuit elements of the system change at the same time, as dictated by the received clock signal. If the clock signal received by a particular clocked element leads or lags that received by another clocked element, race conditions and unpredictable results can occur.
Accordingly, it can be seen that a clock synchronization scheme that can produce a plurality of clock signals synchronized to one another and to a reference (system) clock, and capable of maintaining that synchronization over time, is needed.